boards: phytec: Add support for phyCORE-i.Mx RT1170 and phyBOARD-Atlas i.Mx RT1170

boards/phytec/phyboard_atlas/CMakeLists.txt

@@ -0,0 +1,32 @@
+if(CONFIG_NXP_IMXRT_BOOT_HEADER)
+  zephyr_library()
+  set(RT1170_BOARD_NAME "evkmimxrt1170")
+  set(RT1170_BOARD_DIR
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${RT1170_BOARD_NAME}")
+  if(CONFIG_BOOT_FLEXSPI_NOR)
+    # Include flash configuration block for RT1170 EVK from NXP's HAL.
+    # This configuration block may need modification if another flash chip is
+    # used on your custom board. See NXP AN12238 for more information.
+    zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1)
+    zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
+    zephyr_library_sources(flexspi_nor_config.c)
+  endif()
+  if(CONFIG_EXTERNAL_MEM_CONFIG_DATA)
+    # Include external memory configuration data block for RT1170 EVK from NXP's HAL.
+    # This configuration block may need modification if another SDRAM chip
+    # is used on your custom board.
+    zephyr_compile_definitions(XIP_BOOT_HEADER_XMCD_ENABLE=1)
+    zephyr_library_sources(${RT1170_BOARD_DIR}/xmcd/xmcd.c)
+  else()
+    if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000)
+      message(WARNING "You are using SDRAM as RAM but no external memory"
+        "configuration data (XMCD) is included. This configuration may not boot")
+    endif()
+  endif()
+endif()
+
+if(CONFIG_MCUX_GPT_TIMER)
+  message(WARNING "You appear to be using the GPT hardware timer. "
+    "This timer will enable lower power modes, but at the cost of reduced "
+    "hardware timer resolution")
+endif()

boards/phytec/phyboard_atlas/Kconfig.defconfig

@@ -0,0 +1,44 @@
+# PHYBOARD-ATLAS
+
+# Copyright (c) 2025 PHYTEC America, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_PHYBOARD_ATLAS
+
+# Only use DCD when booting primary core (M7)
+config EXTERNAL_MEM_CONFIG_DATA
+	default y if CPU_CORTEX_M7
+
+config NXP_IMX_EXTERNAL_SDRAM
+	default y if CPU_CORTEX_M7
+
+if SECOND_CORE_MCUX && CPU_CORTEX_M4
+
+config BUILD_OUTPUT_INFO_HEADER
+	default y
+
+DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
+
+# Adjust the offset of the output image if building for RT11xx SOC
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
+	$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
+	$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
+
+endif # SECOND_CORE_MCUX && CPU_CORTEX_M4
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y if CPU_CORTEX_M7 # No cache memory support is required for driver
+
+endif # NETWORKING
+
+if DISK_DRIVERS
+
+config IMX_USDHC_DAT3_PWR_TOGGLE
+	default y
+
+endif # DISK_DRIVERS
+
+endif # BOARD_PHYBOARD_ATLAS

boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas

@@ -0,0 +1,7 @@
+# Copyright 2025 PHYTEC America, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PHYBOARD_ATLAS
+	select SOC_MIMXRT1176_CM7 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM7
+	select SOC_MIMXRT1176_CM4 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM4
+	select SOC_PART_NUMBER_MIMXRT1176DVMAA

boards/phytec/phyboard_atlas/board.cmake

@@ -0,0 +1,18 @@
+if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX)
+ board_runner_args(pyocd "--target=mimxrt1170_cm7")
+ board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load")
+
+ board_runner_args(linkserver  "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK")
+ board_runner_args(linkserver "--core=cm7")
+elseif(CONFIG_SOC_MIMXRT1176_CM4)
+ board_runner_args(pyocd "--target=mimxrt1170_cm4")
+ # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
+ board_runner_args(jlink "--device=MIMXRT1176xxxA_M4")
+
+ board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK")
+ board_runner_args(linkserver "--core=cm4")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)

boards/phytec/phyboard_atlas/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: phyboard_atlas
+  full_name: phyBOARD-Atlas i.MX RT1170
+  vendor: phytec
+  socs:
+    - name: mimxrt1176

boards/phytec/phyboard_atlas/flexspi_nor_config.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2025 PHYTEC America, LLC
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <flexspi_nor_config.h>
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+#define FLASH_DUMMY_CYCLES 0x06
+#define FLASH_DUMMY_VALUE  0x06
+
+const struct flexspi_nor_config_t qspiflash_config = {
+	.memConfig = {
+			.tag = FLEXSPI_CFG_BLK_TAG,
+			.version = FLEXSPI_CFG_BLK_VERSION,
+			.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+			.csHoldTime = 3u,
+			.csSetupTime = 3u,
+			.controllerMiscOption = 0x10,
+			.deviceType = kFlexSpiDeviceType_SerialNOR,
+			.sflashPadType = kSerialFlash_4Pads,
+			.serialClkFreq = kFlexSpiSerialClk_100MHz,
+			.sflashA1Size = 16u * 1024u * 1024u,
+			.configCmdEnable = 1u,
+			.configModeType[0] = kDeviceConfigCmdType_Generic,
+			.configCmdSeqs[0] = {
+					.seqNum = 1,
+					.seqId = 12,
+					.reserved = 0,
+				},
+			.configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3),
+			.lookupTable = {
+					/* Fast read quad mode - SDR */
+					[4 * CMD_LUT_SEQ_IDX_READ + 0] =
+						FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB,
+								RADDR_SDR, FLEXSPI_4PAD, 0x18),
+					[4 * CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
+						DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES,
+						READ_SDR, FLEXSPI_4PAD, 0x04),
+
+					/* Read Status LUTs */
+					[4 * CMD_LUT_SEQ_IDX_READSTATUS + 0] =
+						FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
+								READ_SDR, FLEXSPI_1PAD, 0x04),
+
+					/* Write Enable LUTs */
+					[4 * CMD_LUT_SEQ_IDX_WRITEENABLE + 0] =
+						FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP,
+								FLEXSPI_1PAD, 0x0),
+
+					/* Page Program LUTs */
+					[4 * CMD_LUT_SEQ_IDX_WRITE + 0] =
+						FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02,
+								RADDR_SDR, FLEXSPI_1PAD, 0x18),
+					[4 * CMD_LUT_SEQ_IDX_WRITE + 1] =
+						FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP,
+								FLEXSPI_1PAD, 0x0),
+				},
+		},
+	.pageSize = 256u,
+	.sectorSize = 4u * 1024u,
+	.ipcmdSerialClkFreq = 0x1,
+	.blockSize = 64u * 1024u,
+	.isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */