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Add support for cadence SPI #87382

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Introduces the Cadence SPI IP driver and dt bindings. By adding support for master mode, the SPI controller enables the communications with variety of peripherals such as SPI-NOR flash memories, eeprom and Trusted Platform Module(TPM) devices and other peripherals. Additionally, the controller can operate in an external loopback test mode

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Add devicetree binding for the Cadence SPI IP.

Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Message-ID: <20250319100832.3986031-2-srikanth.boyapally@amd.com>
State: pending
mm_reg_t base;
void (*irq_config_func)(const struct device *dev);
uint8_t num_ss_bits;
uint32_t is_decoded_cs;
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Change this 2 attributes to uint6_t, for better alignment.

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made changes as per you suggested

};

struct cdns_spi_data {
uint16_t slave;
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move it at the end

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Done

cdns_spi_cs_cntrl(dev, true);

#ifdef CONFIG_CDNS_SPI_INTR
do {
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in this case, fifo r/w should happen in the isr. Or else, here it's going to do a back & forth between isr/user thread etc etc... thus more overhead.

It should just enable the interrupt, and wait for completion.

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Hi @tbursztyka
Thanks for the review.

changed the logic as per your suggestion.

Introduces the Cadence SPI IP driver. By adding support for master mode,
the SPI controller enables the communications with variety of peripherals
such as SPI-NOR flash memories, eeprom and Trusted Platform Module(TPM)
devices and other peripherals. Additionally, the controller can operate
in an external loopback test mode.

Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Message-ID: <20250319100832.3986031-3-srikanth.boyapally@amd.com>
State: pending
@tbursztyka
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Just realized @XenuIsWatching has made a previous PR about the same hw, in #85973

You'll need to sync. My position would be : first come first served.

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3 participants