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STM32N6: Add SDMMC support #87575

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STM32N6: Add SDMMC support #87575

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7330c73
drivers: disk: stm32 sdmmc: add stm32n6 support
gautierg-st Jul 4, 2024
519d4c0
dts: arm: st: n6: add sdmmc nodes
gautierg-st Jan 28, 2025
4740f1b
boards: st: stm32n6570_dk: configure and enable sdmmc2
gautierg-st Feb 14, 2025
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6 changes: 6 additions & 0 deletions boards/st/stm32n6570_dk/doc/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,12 @@ Default Zephyr Peripheral Mapping:
- I2C4_SDA : PE14
- LD1 : PO1
- LD2 : PG10
- SDMMC2_CK : PC2
- SDMMC2_CMD : PC3
- SDMMC2_D0 : PC4
- SDMMC2_D1 : PC5
- SDMMC2_D2 : PC0
- SDMMC2_D3 : PE4
- SPI5_SCK : PE15
- SPI5_MOSI : PG2
- SPI5_MISO : PH8
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28 changes: 28 additions & 0 deletions boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
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Expand Up @@ -59,6 +59,15 @@
status = "okay";
};

&pll2 {
clocks = <&clk_hsi>;
div-m = <4>;
mul-n = <24>;
div-p1 = <2>;
div-p2 = <2>;
status = "okay";
};

&ic1 {
pll-src = <1>;
ic-div = <2>;
Expand All @@ -71,6 +80,12 @@
status = "okay";
};

&ic4 {
pll-src = <2>;
ic-div = <2>;
status = "okay";
};

&ic6 {
pll-src = <1>;
ic-div = <2>;
Expand Down Expand Up @@ -140,6 +155,19 @@
status = "okay";
};

&sdmmc2 {
status = "okay";
clocks = <&rcc STM32_CLOCK(AHB5, 7)>,
<&rcc STM32_SRC_IC4 SDMMC2_SEL(2)>;
pinctrl-0 = <&sdmmc2_d0_pc4 &sdmmc2_d1_pc5
&sdmmc2_d2_pc0 &sdmmc2_d3_pe4
&sdmmc2_ck_pc2 &sdmmc2_cmd_pc3>;
pinctrl-names = "default";
bus-width = <4>;
cd-gpios = <&gpion 8 GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpioq 7 GPIO_ACTIVE_HIGH>;
};

&spi5 {
clocks = <&rcc STM32_CLOCK(APB2, 20)>,
<&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
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3 changes: 2 additions & 1 deletion drivers/disk/Kconfig.sdmmc
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Expand Up @@ -51,7 +51,8 @@ config SDMMC_STM32_HWFC
SOC_SERIES_STM32H7X || \
SOC_SERIES_STM32F7X || \
SOC_SERIES_STM32L4X || \
SOC_SERIES_STM32L5X
SOC_SERIES_STM32L5X || \
SOC_SERIES_STM32N6X
help
Enable SDMMC Hardware Flow Control to avoid FIFO underrun (TX mode) and
overrun (RX mode) errors.
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18 changes: 18 additions & 0 deletions dts/arm/st/n6/stm32n6.dtsi
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Expand Up @@ -663,6 +663,24 @@
};
};

sdmmc1: sdmmc@58027000 {
compatible = "st,stm32-sdmmc";
reg = <0x58027000 0x1000>;
clocks = <&rcc STM32_CLOCK(AHB5, 8)>;
resets = <&rctl STM32_RESET(AHB5, 8)>;
interrupts = <174 0>;
status = "disabled";
};

sdmmc2: sdmmc@58026800 {
compatible = "st,stm32-sdmmc";
reg = <0x58026800 0x400>;
clocks = <&rcc STM32_CLOCK(AHB5, 7)>;
resets = <&rctl STM32_RESET(AHB5, 7)>;
interrupts = <175 0>;
status = "disabled";
};

xspi1: xspi@58025000 {
compatible = "st,stm32-xspi";
reg = <0x58025000 0x1000>;
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