[GPU] Periodic Coverity roundup

src/gpu/gpu_reorder_pd.cpp

@@ -47,7 +47,7 @@ status_t gpu_reorder_pd_t::maybe_create_zp_precompute_conv_pd(
     auto gpu_align = utils::downcast<gpu::engine_t *>(dst_engine)
                              ->get_buffer_alignment();
     auto scratchpad = scratchpad_registry().registrar();
-    auto registry = zp_precomp_conv_pd_->scratchpad_registry();
+    const auto &registry = zp_precomp_conv_pd_->scratchpad_registry();
     memory_desc_wrapper wspace((is_bwd_d) ? zp_precomp_conv_pd_->diff_dst_md()
                                           : zp_precomp_conv_pd_->src_md());
     scratchpad.book(key_conv_tr_src, wspace.size(), 1, gpu_align);

src/gpu/gpu_resource.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2020-2024 Intel Corporation
+* Copyright 2020-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -33,6 +33,7 @@ struct gpu_resource_t : public resource_t {
     using mapped_memory_t = std::unique_ptr<memory_storage_t>;
 
     gpu_resource_t() = default;
+    ~gpu_resource_t() override = default;
 
     void add_memory_storage(key_memory_t idx, mapped_memory_t &&m) {
         assert(idx_to_memory_storage_.count(idx) == 0);

src/gpu/intel/compute/kernel.hpp

@@ -246,6 +246,7 @@ class kernel_bundle_t {
     kernel_bundle_t &operator=(const kernel_bundle_t &other) = delete;
     kernel_bundle_t(kernel_bundle_t &&other) = default;
     kernel_bundle_t &operator=(kernel_bundle_t &&other) = default;
+    ~kernel_bundle_t() = default;
 
     status_t get_kernels(std::vector<kernel_t> &kernels,
             const std::vector<const char *> &kernel_names) const {

src/gpu/intel/compute/kernel_arg_list.hpp

@@ -229,6 +229,7 @@ class kernel_arg_t {
 class kernel_arg_list_t {
 public:
     kernel_arg_list_t() { args_.reserve(512); }
+    ~kernel_arg_list_t() = default;
 
     void append(const memory_storage_t &storage) {
         args_.emplace_back();

src/gpu/intel/jit/codegen/codegen.cpp

@@ -755,7 +755,7 @@ class ir_to_ngen_t : public ir_visitor_t {
         auto do_eltwise = [&](const reg_buf_data_t &r, const int count) {
             if (func.alg_kind == alg_kind::eltwise_stochastic_round) {
                 gpu_assert(args.size() == 3);
-                auto seed = args[2].reg_buf_data();
+                const auto &seed = args[2].reg_buf_data();
                 inj.compute(ngen::GRFRange(r.base(), count),
                         seed.reg_data().getBase(), seed.reg_data().getOffset(),
                         func.dst_dt);

src/gpu/intel/jit/codegen/reduce.hpp

@@ -133,7 +133,7 @@ class reduce_impl_t {
                 auto a_blocks = a.blocks();
                 a_blocks.erase(a_blocks.begin());
                 a = layout_t(a.type(), a.ndims(), 0, a_blocks);
-                return find_1d_tile(a, b);
+                return find_1d_tile(std::move(a), std::move(b));
             }
             return tensor_t(std::vector<dim_t>(b.ndims(), 1));
         }

src/gpu/intel/jit/conv/config.cpp

@@ -646,9 +646,9 @@ void init_data_tags(const conv_config_t &cfg, const memory_desc_t &src_md,
 
     // Use plain tags for user-facing activations for small-channel tensors.
     if (!matches_tag(src_md, src_tag) && is_small_ic_g1)
-        user_src_tag = (user_src_req.empty() ? "axb" : std::move(user_src_req));
+        user_src_tag = (user_src_req.empty() ? "axb" : user_src_req);
     if (!matches_tag(dst_md, dst_tag) && is_small_oc_g1)
-        user_dst_tag = (user_dst_req.empty() ? "axb" : std::move(user_dst_req));
+        user_dst_tag = (user_dst_req.empty() ? "axb" : user_dst_req);
 
     // Avoid reorder for small shapes
     if (!user_src_tag.empty() && !user_dst_tag.empty() && prb.g == 1
@@ -1118,7 +1118,7 @@ bool post_op_layouts_ok(const conv_problem_t &prb) {
                             po.binary.src1_desc.dims, prb.ndims, true);
             // These cases don't have message-related limitations.
             if ((mask & (1 << 1)) == 0 || mask == (1 << 1)) continue;
-            auto rhs_layout = po.is_prelu()
+            const auto &rhs_layout = po.is_prelu()
                     ? layout_t(type_t::f32(), 0,
                             get_prelu_weights_dims(po.prelu.mask, output_md))
                     : layout_t(po.binary.src1_desc);
@@ -1568,12 +1568,13 @@ class mn_walker_t {
         : prb_(prb) {
         for (auto &d : tile) {
             auto bmnk = to_gemm(d, prb);
-            entry_t e;
+            if (!utils::one_of(bmnk, pvars::m, pvars::n)) continue;
+
+            entries_.emplace_back();
+            entry_t &e = entries_.back();
             e.dim = d;
             e.tile_size = tile[d];
-            if (!utils::one_of(bmnk, pvars::m, pvars::n)) continue;
             e.mn_kind = (bmnk == pvars::m ? 'm' : 'n');
-            entries_.push_back(e);
         }
         // Put through spatial dimensions first and order spatial accordingly
         // (WHD, width is first).

src/gpu/intel/jit/conv/ir_builder.cpp

@@ -644,13 +644,13 @@ stmt_t inject_compute_loop_label(const stmt_t &s) {
 }
 
 void conv_ir_builder_t::build() {
-    auto &prb = cfg_.prb();
+    const auto &prb = cfg_.prb();
 
     trace_reset();
 
     std::vector<stmt_t> init_stmts;
-    auto &plan = cfg_.plan();
-    auto gemm_schedule = plan.gemm_schedule;
+    const auto &plan = cfg_.plan();
+    const auto &gemm_schedule = plan.gemm_schedule;
     auto init_cset = plan.init_cset;
     init_kernel_grid(cfg_.kernel_grid(), cfg_.thread_group_grid(), cfg_.simd(),
             init_cset, init_stmts);

src/gpu/intel/jit/conv/message_patterns.hpp

@@ -137,7 +137,7 @@ struct conv_stride_layout_t : public stride_layout_t<pvar_t> {
                                     || prb.id < prb.od * prb.sd
                                                     + (prb.kd - 1)
                                                             * (prb.dd + 1));
-                    auto x_dim = !prb.is_bwd_d ? pvars::od : pvars::id;
+                    const auto &x_dim = !prb.is_bwd_d ? pvars::od : pvars::id;
                     auto x = !prb.is_bwd_d ? prb.od : prb.id;
                     auto xas = !prb.is_bwd_d ? prb.sd : prb.sd == 1;
                     auto kx = prb.kd;
@@ -151,7 +151,7 @@ struct conv_stride_layout_t : public stride_layout_t<pvar_t> {
                                     || prb.ih < prb.oh * prb.sh
                                                     + (prb.kh - 1)
                                                             * (prb.dh + 1));
-                    auto x_dim = !prb.is_bwd_d ? pvars::oh : pvars::ih;
+                    const auto &x_dim = !prb.is_bwd_d ? pvars::oh : pvars::ih;
                     auto x = !prb.is_bwd_d ? prb.oh : prb.ih;
                     auto xas = !prb.is_bwd_d ? prb.sh : prb.sh == 1;
                     auto kx = prb.kh;
@@ -163,7 +163,7 @@ struct conv_stride_layout_t : public stride_layout_t<pvar_t> {
                         && (prb.pw
                                 || prb.iw < prb.ow * prb.sw
                                                 + (prb.kw - 1) * (prb.dw + 1));
-                auto x_dim = !prb.is_bwd_d ? pvars::ow : pvars::iw;
+                const auto &x_dim = !prb.is_bwd_d ? pvars::ow : pvars::iw;
                 auto x = !prb.is_bwd_d ? prb.ow : prb.iw;
                 auto xas = !prb.is_bwd_d ? prb.sw : prb.sw == 1;
                 auto kx = prb.kw;

src/gpu/intel/jit/conv/pipeline.cpp

@@ -278,7 +278,7 @@ class compute_step_t {
             }
             auto let_info = create_let_info(
                     let, is_preload_let(_let), is_mul_let(_let));
-            let_infos.push_back(let_info);
+            let_infos.push_back(std::move(let_info));
             seen.insert(_let);
         };
         for (auto &_let : inner_let_stmts_)
@@ -622,9 +622,9 @@ struct compute_params_t {
         : slm_bufs(slm_bufs)
         , gmem_bufs(gmem_bufs)
         , slm_buf_size(slm_buf_size)
-        , prefetch_bufs(prefetch_bufs) {
-        use_slm = (slm_buf_size > 0);
-        use_prefetch = (prefetch_bufs > 0);
+        , prefetch_bufs(prefetch_bufs)
+        , use_slm(slm_buf_size > 0)
+        , use_prefetch(prefetch_bufs > 0) {
         gpu_assert(!use_slm || !use_prefetch)
                 << "Can't have both SLM buffering and prefetch enabled.";
         if (use_slm) {

src/gpu/intel/jit/conv/plan.cpp

@@ -282,8 +282,8 @@ void init_fwd(const conv_config_t &cfg_, gemm_schedule_t &gemm_schedule,
 
     std::vector<expr_t> kernel_grid_vars;
     kernel_grid_vars.push_back(oc_tile.grid_idx());
-    kernel_grid_vars.push_back(od);
-    kernel_grid_vars.push_back(oh);
+    kernel_grid_vars.push_back(std::move(od));
+    kernel_grid_vars.push_back(std::move(oh));
     kernel_grid_vars.push_back(ow_tile.grid_idx());
     kernel_grid_vars.push_back(g_tile.grid_idx());
     kernel_grid_vars.push_back(mb_tile.grid_idx());
@@ -661,8 +661,8 @@ void init_bwd_w(const conv_config_t &cfg_, gemm_schedule_t &gemm_schedule,
     kernel_grid_vars.push_back(od_tile.grid_idx());
     kernel_grid_vars.push_back(oh_tile.grid_idx());
     kernel_grid_vars.push_back(ow_tile.grid_idx());
-    kernel_grid_vars.push_back(kd);
-    kernel_grid_vars.push_back(kh);
+    kernel_grid_vars.push_back(std::move(kd));
+    kernel_grid_vars.push_back(std::move(kh));
     kernel_grid_vars.push_back(kw_tile.grid_idx());
     kernel_grid_vars.push_back(ic_tile.grid_idx());
     kernel_grid_vars.push_back(mb_tile.grid_idx());
@@ -1263,17 +1263,16 @@ struct fma_layout_hint_t {
 };
 
 struct fma_context_t {
-    fma_context_t(const conv_config_t &cfg) {
-        hw = cfg.hw();
-        simd = cfg.simd();
-        vec_size = cfg.vec_size();
-        fma = cfg.fma_kind();
-        a_type = type_t(cfg.prb().a_data_type);
-        b_type = type_t(cfg.prb().b_data_type);
-        acc_type = get_accumulation_type(cfg, a_type, b_type);
-        is_src1_broadcast = !cfg.prb().is_dw;
-        ab_swap_transpose_ = cfg.prb().ab_swap_transpose;
-    }
+    fma_context_t(const conv_config_t &cfg)
+        : hw(cfg.hw())
+        , simd(cfg.simd())
+        , vec_size(cfg.vec_size())
+        , fma(cfg.fma_kind())
+        , a_type(cfg.prb().a_data_type)
+        , b_type(cfg.prb().b_data_type)
+        , acc_type(get_accumulation_type(cfg, a_type, b_type))
+        , is_src1_broadcast(!cfg.prb().is_dw)
+        , ab_swap_transpose_(cfg.prb().ab_swap_transpose) {}
 
     fma_layout_hint_t &layout_hint(abc_kind_t abc) {
         return (abc == abc_kind_t::a) ? a_layout_hint : b_layout_hint;
@@ -2167,7 +2166,7 @@ class plan_builder_t {
 
         auto &direct_view
                 = (abc == abc_kind_t::a ? a_direct_view_ : b_direct_view_);
-        auto load_view = direct_view ? direct_view.get() : gmem_view;
+        const auto &load_view = direct_view ? direct_view.get() : gmem_view;
 
         auto params = get_send_params(cfg_.exec_cfg(), send_op_t::load,
                 send_address_t::a64, cfg_.fma_kind(), abc, load_view,

src/gpu/intel/jit/conv/tiler.cpp

@@ -360,7 +360,7 @@ class conv_blocking_scheme_t : public blocking_scheme_t {
         x2_info.set_iter_unit(unit);
         x2_info.d0 = info0.div_info;
         x2_info.d1 = info1.div_info;
-        x2_tile_infos_.push_back(x2_info);
+        x2_tile_infos_.push_back(std::move(x2_info));
     }
 
     void finalize_loop_dims(const conv_config_t &cfg) {
@@ -395,7 +395,7 @@ class conv_blocking_scheme_t : public blocking_scheme_t {
                 ld.size = shape.get(d, 1);
                 if (iter_.has(d))
                     ld.size = utils::div_up(ld.size, iter_dim_hint);
-                loop_dims.push_back(ld);
+                loop_dims.push_back(std::move(ld));
             }
             std::sort(loop_dims.begin(), loop_dims.end(),
                     [&](const loop_dim_t &a, const loop_dim_t &b) {
@@ -597,7 +597,8 @@ class conv_blocking_checker_t : public blocking_checker_t {
 
 private:
     struct context_t {
-        context_t(const blocking_t &blk, const conv_config_t &cfg) : blk(blk) {
+        context_t(const blocking_t &blk, const conv_config_t &cfg)
+            : blk(blk), dpas_2x_depth(get_dpas_2x_depth(blk, cfg)) {
             auto &prb = cfg.prb();
             auto gemm_iter = to_gemm(blk.iter(), prb);
             auto gemm_loop = to_gemm(blk.loop(), prb);
@@ -611,7 +612,6 @@ class conv_blocking_checker_t : public blocking_checker_t {
             m_tg = gemm_tg.get(pvars::m, 1);
             n_tg = gemm_tg.get(pvars::n, 1);
             k_tg = gemm_tg.get(pvars::k, 1);
-            dpas_2x_depth = get_dpas_2x_depth(blk, cfg);
         }
 
         bool get_dpas_2x_depth(
@@ -1111,7 +1111,7 @@ conv_blocking_scheme_list_t get_blocking_schemes_fwd(const conv_config_t &cfg) {
 conv_blocking_scheme_list_t get_blocking_schemes_bwd_d(
         const conv_config_t &cfg) {
     conv_blocking_scheme_list_t ret(conv_tune_level());
-    auto m_iter_dim = cfg.prb().ab_swap_transpose
+    const auto &m_iter_dim = cfg.prb().ab_swap_transpose
             ? pvars::ic
             : select_iter_dim(cfg, {pvars::mb, pvars::iw});
     bool m_is_mb = (m_iter_dim == pvars::mb);

src/gpu/intel/jit/conv/zp_plan.cpp

@@ -766,7 +766,7 @@ class zp_comp_init_plan_t : public base_plan_t {
                 buf_mgr, zp_type, real_zp, (zp_stride) ? simd_ : 1);
         auto mad = mad_t::make(
                 hw, comp_type, simd_, zp_type, zp_stride, wei_type, wei_stride);
-        return ret.append(mad.call({comp, comp, real_zp, wei}));
+        return ret.append(mad.call({comp, comp, std::move(real_zp), wei}));
     }
 
     stmt_t maybe_typecast_zp_src(buffer_manager_t &buf_mgr, type_t &type,
@@ -937,7 +937,7 @@ struct texpr_t {
             auto s = "_" + std::to_string(vidxs[i]);
             // NOLINTNEXTLINE(performance-inefficient-string-concatenation)
             if (vstrides[i] != 1) s = std::to_string(vstrides[i]) + " x " + s;
-            parts.push_back(s);
+            parts.push_back(std::move(s));
         }
         for (int i = 0; i < (int)parts.size(); i++) {
             if (i > 0) oss << " + ";
@@ -1123,7 +1123,7 @@ class zp_mask_init_plan_t : public base_plan_t {
                     for (auto &m : mask_descs_) {
                         auto e_m = m.normalize(
                                 vvars_, vstart_, start, simd_, simd_dim_idx_);
-                        e_masks.push_back(e_m);
+                        e_masks.push_back(std::move(e_m));
                     }
                     auto cond = e_masks[0];
                     for (int i = 1; i < (int)e_masks.size(); i++)

src/gpu/intel/jit/gemm/generator/pieces/c_update.cxx

@@ -1078,9 +1078,9 @@ void BLASKernelGenerator<hw>::updateCLayout(const vector<RegisterBlock> &layoutE
                             break;
                         case 1:
                             {
-                                C_accs.push_back(C_acc);
-                                C_accSwaps.push_back(C_accSwap);
-                                C_loads.push_back(C_load);
+                                C_accs.push_back(std::move(C_acc));
+                                C_accSwaps.push_back(std::move(C_accSwap));
+                                C_loads.push_back(std::move(C_load));
                             }
                             break;
                         case 2:

src/gpu/intel/jit/ir/blocking.cpp

@@ -196,7 +196,7 @@ std::vector<blocking_t> level_tile_set_t::sample(int target,
             set(blk, dims_[i], try_tiles[i]);
         }
         if (!is_ok(blk)) continue;
-        ret.push_back(blk);
+        ret.push_back(std::move(blk));
         if ((int)ret.size() >= target) break;
     }
     return ret;

src/gpu/intel/jit/ir/core.hpp

@@ -600,6 +600,8 @@ class ref_count_t {
 public:
     ref_count_t() : value_(0) {}
     ref_count_t(const ref_count_t &) = delete;
+    ref_count_t &operator=(const ref_count_t &) = delete;
+    ~ref_count_t() = default;
 
     uint32_t increment() { return ++value_; }
     uint32_t decrement() { return --value_; }
@@ -627,6 +629,7 @@ class object_impl_t {
     object_impl_t(type_info_t type_info) : type_info_(type_info) {};
 
     object_impl_t(const object_impl_t &) = delete;
+    object_impl_t &operator=(const object_impl_t &) = delete;
 
     virtual ~object_impl_t() = default;
 
@@ -866,6 +869,7 @@ class ir_mutator_t {
     template <typename T>
     std::vector<T> mutate(const std::vector<T> &v) {
         std::vector<T> new_v;
+        new_v.reserve(v.size());
         for (auto &e : v)
             new_v.push_back(mutate(e));
         return new_v;

src/gpu/intel/jit/ir/epilogue.cpp

@@ -367,7 +367,7 @@ class post_op_tensor_t {
 
         reg_layout_ = slm_reduce_builder_.reg_layout();
 
-        auto new_tile = slm_reduce_builder_.thr_tile();
+        const auto &new_tile = slm_reduce_builder_.thr_tile();
         info_ = info_.create_sub_tensor(new_tile);
 
         auto &slm_allocs = slm_reduce_builder_.allocs();
@@ -740,7 +740,7 @@ class epilogue_builder_t {
                 gpu_assert(c_po_idx_ == -1);
                 c_po_idx_ = tensor_idx;
             }
-            post_op_tensors_.push_back(po_tensor);
+            post_op_tensors_.push_back(std::move(po_tensor));
             tensor_idx++;
         }
 
@@ -1030,6 +1030,7 @@ class epilogue_builder_t {
 
         // Create sub-tensors for post-ops.
         std::vector<post_op_tensor_t> sub_po_tensors;
+        sub_po_tensors.reserve(post_op_tensors_.size());
         for (auto &t : post_op_tensors_)
             sub_po_tensors.push_back(t.create_sub_tensor(tile));
 

src/gpu/intel/jit/ir/ir.cpp

@@ -387,7 +387,7 @@ class alloc_injector_t : public ir_mutator_t {
         buf_total_refs_ = buf_cur_refs_;
         for (auto &kv : buf_cur_refs_)
             kv.second = 0;
-        in_ctor_ = false;
+        in_ctor_ = false; // NOLINT(cppcoreguidelines-prefer-member-initializer)
     }
 
 #define HANDLE_IR_OBJECT(type) \
@@ -473,7 +473,7 @@ class alloc_injector_t : public ir_mutator_t {
             j = _find(j);
             parent[j] = i;
         };
-        std::vector<stmt_t> new_stmt_seq = stmt_vec;
+        std::vector<stmt_t> new_stmt_seq = std::move(stmt_vec);
         for (auto &buf : bufs) {
             auto &e = entries.at(buf);
             stmt_t stmt;

src/gpu/intel/jit/ir/kernel_info.hpp

@@ -40,6 +40,8 @@ class memory_storage_ptr_t {
         : unique_ptr_(std::move(ptr)) {}
     memory_storage_ptr_t(const memory_storage_t *ptr) : raw_ptr_(ptr) {}
     memory_storage_ptr_t(const memory_storage_ptr_t &) = delete;
+    memory_storage_ptr_t &operator=(const memory_storage_ptr_t &) = delete;
+    ~memory_storage_ptr_t() = default;
 
     const memory_storage_t *get() const {
         if (unique_ptr_) return unique_ptr_.get();