cpu: clang-tidy: bunch of renames and small updates

src/cpu/cpu_primitive.hpp

@@ -29,6 +29,9 @@
 
 #include "cpu/ref_io_helper.hpp"
 
+//NOLINTBEGIN(bugprone-macro-parentheses)
+// These macros are actual pieces of code, can't put certain pieces into `()`.
+// TODO: consider making them functions.
 #define DEFINE_ARG_SCALES_BUFFER_ATTR(attr, scales, arg) \
     alignas(16) float CONCAT2(scales, _buf16)[16] = {0}; \
     const float *scales {nullptr}; \
@@ -37,18 +40,19 @@
             utils::array_set(CONCAT2(scales, _buf16), 1.0f, 16); \
             scales = CONCAT2(scales, _buf16); \
         } else { \
-            scales = CTX_IN_MEM(const float *, DNNL_ARG_ATTR_SCALES | arg); \
+            scales = CTX_IN_MEM(const float *, DNNL_ARG_ATTR_SCALES | (arg)); \
             VCHECK_ATTR(scales != nullptr, \
-                    "Scales buffer for arg %d is missing", arg); \
-            const auto scales_d = ctx.memory_mdw(DNNL_ARG_ATTR_SCALES | arg); \
+                    "Scales buffer for arg %d is missing", (arg)); \
+            const auto scales_d \
+                    = ctx.memory_mdw(DNNL_ARG_ATTR_SCALES | (arg)); \
             VCHECK_ATTR( \
                     utils::one_of(scales_d.data_type(), data_type::f32, \
                             data_type::f16, data_type::bf16, data_type::e8m0), \
                     "Unsupported scales data type"); \
             if (scales_d.nelems() == 1) { \
                 const float s = cpu::io::load_float_value( \
                         scales_d.data_type(), scales, 0); \
-                if (utils::one_of(arg, DNNL_ARG_DST, \
+                if (utils::one_of((arg), DNNL_ARG_DST, \
                             DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_DST)) { \
                     utils::array_set(CONCAT2(scales, _buf16), 1.f / s, 16); \
                 } else { \
@@ -61,7 +65,7 @@
     MAYBE_UNUSED(scales);
 
 #define DEFINE_ARG_SCALES_BUFFER(scales, arg) \
-    DEFINE_ARG_SCALES_BUFFER_ATTR(pd()->attr(), scales, arg)
+    DEFINE_ARG_SCALES_BUFFER_ATTR(pd()->attr(), scales, (arg))
 
 #define DEFINE_ZERO_POINTS_BUFFER_ATTR(attr, zero_points_ptr, arg) \
     int32_t CONCAT2(default_zero_point_, arg) = 0; \
@@ -74,11 +78,11 @@
              * Accessing `zero_points_ptr` by index will lead to a crash for
              * datatypes different from s32. */ \
             zero_points_ptr = CTX_IN_MEM( \
-                    const int32_t *, DNNL_ARG_ATTR_ZERO_POINTS | arg); \
+                    const int32_t *, DNNL_ARG_ATTR_ZERO_POINTS | (arg)); \
             VCHECK_ATTR(zero_points_ptr != nullptr, \
-                    "Zero points buffer for arg %d is missing", arg); \
+                    "Zero points buffer for arg %d is missing", (arg)); \
             const auto zero_points_d \
-                    = ctx.memory_mdw(DNNL_ARG_ATTR_ZERO_POINTS | arg); \
+                    = ctx.memory_mdw(DNNL_ARG_ATTR_ZERO_POINTS | (arg)); \
             VCHECK_ATTR(utils::one_of(zero_points_d.data_type(), \
                                 data_type::s32, data_type::s8, data_type::u8, \
                                 data_type::s4, data_type::u4), \
@@ -132,4 +136,6 @@
 #define DEFINE_ZERO_POINT_VALUE(zero_point, mem_arg) \
     DEFINE_ZERO_POINT_VALUE_ATTR(pd()->attr(), zero_point, mem_arg)
 
+//NOLINTEND(bugprone-macro-parentheses)
+
 #endif // CPU_CPU_PRIMITIVE_HPP

src/cpu/cpu_stream.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2019-2024 Intel Corporation
+* Copyright 2019-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -34,7 +34,7 @@ namespace cpu {
 struct cpu_stream_t : public stream_t {
     cpu_stream_t(engine_t *engine, impl::stream_impl_t *stream_impl)
         : stream_t(engine, stream_impl) {}
-    virtual ~cpu_stream_t() = default;
+    ~cpu_stream_t() override = default;
 
     dnnl::impl::status_t wait() override {
         // CPU execution is synchronous so return immediately

src/cpu/platform.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2020-2024 Intel Corporation
+* Copyright 2020-2025 Intel Corporation
 * Copyright 2020-2024 FUJITSU LIMITED
 * Copyright 2022-2024 Arm Ltd. and affiliates
 *
@@ -258,9 +258,9 @@ unsigned get_max_threads_to_use() {
 int get_vector_register_size() {
 #if DNNL_X64
     using namespace x64;
-    if (mayiuse(avx512_core)) return cpu_isa_traits<avx512_core>::vlen;
-    if (mayiuse(avx)) return cpu_isa_traits<avx>::vlen;
-    if (mayiuse(sse41)) return cpu_isa_traits<sse41>::vlen;
+    if (mayiuse(avx512_core)) return cpu_isa_traits_t<avx512_core>::vlen;
+    if (mayiuse(avx)) return cpu_isa_traits_t<avx>::vlen;
+    if (mayiuse(sse41)) return cpu_isa_traits_t<sse41>::vlen;
 #elif DNNL_AARCH64
     using namespace aarch64;
     if (mayiuse(asimd)) return cpu_isa_traits<asimd>::vlen;

src/cpu/ref_batch_normalization.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2016-2024 Intel Corporation
+* Copyright 2016-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -158,8 +158,8 @@ status_t ref_batch_normalization_fwd_t<d_type>::execute_forward(
                 }
             }
             if (d_type == s8)
-                dst[d_off]
-                        = q10n::qz_a1b0<float, data_t>()(maybe_post_op(bn_res));
+                dst[d_off] = q10n::qz_a1b0_t<float, data_t>()(
+                        maybe_post_op(bn_res));
             else
                 dst[d_off] = maybe_post_op(bn_res);
         }

src/cpu/ref_concat.hpp

@@ -109,7 +109,7 @@ struct ref_concat_t : public primitive_t {
         return status::success;
     }
 
-    ~ref_concat_t() = default;
+    ~ref_concat_t() override = default;
 
     status_t execute(const exec_ctx_t &ctx) const override {
         using namespace memory_tracking::names;

src/cpu/ref_deconvolution.hpp

@@ -102,8 +102,6 @@ struct ref_deconvolution_fwd_t : public primitive_t {
             , dst_tag_(other.dst_tag_)
             , name_(other.name_) {}
 
-        ~pd_t() = default;
-
         DECLARE_COMMON_PD_T(name_.c_str(), ref_deconvolution_fwd_t);
 
         status_t init_convolution(engine_t *engine) {
@@ -335,8 +333,6 @@ struct ref_deconvolution_bwd_data_t : public primitive_t {
             , conv_pd_(other.conv_pd_->clone())
             , name_(other.name_) {}
 
-        ~pd_t() = default;
-
         DECLARE_COMMON_PD_T(name_.c_str(), ref_deconvolution_bwd_data_t);
 
         status_t init_convolution(engine_t *engine) {
@@ -446,8 +442,6 @@ struct ref_deconvolution_bwd_weights_t : public primitive_t {
             , dst_tag_(other.dst_tag_)
             , name_(other.name_) {}
 
-        ~pd_t() = default;
-
         DECLARE_COMMON_PD_T(name_.c_str(), ref_deconvolution_bwd_weights_t);
 
         status_t init_convolution(engine_t *engine) {

src/cpu/ref_resampling.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2019-2024 Intel Corporation
+* Copyright 2019-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -67,7 +67,8 @@ struct ref_resampling_fwd_t : public primitive_t {
     };
 
     ref_resampling_fwd_t(const pd_t *apd);
-    ~ref_resampling_fwd_t();
+
+    ~ref_resampling_fwd_t() override;
 
     status_t init(engine_t *engine) override {
         ref_post_ops_
@@ -114,7 +115,8 @@ struct ref_resampling_bwd_t : public primitive_t {
     };
 
     ref_resampling_bwd_t(const pd_t *apd);
-    ~ref_resampling_bwd_t();
+
+    ~ref_resampling_bwd_t() override;
 
     status_t execute(const exec_ctx_t &ctx) const override {
         execute_backward(ctx);

src/cpu/ref_shuffle.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2018-2024 Intel Corporation
+* Copyright 2018-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -92,7 +92,7 @@ struct ref_shuffle_t : public primitive_t {
         return dnnl_success;
     }
 
-    ~ref_shuffle_t() { free(rev_transposed_); }
+    ~ref_shuffle_t() override { free(rev_transposed_); }
 
     status_t execute(const exec_ctx_t &ctx) const override {
         const memory_desc_wrapper src_d(

src/cpu/reorder/simple_reorder.hpp

@@ -46,10 +46,10 @@ template <impl::data_type_t type>
 using data_t = typename prec_traits_t<type>::type;
 
 template <impl::data_type_t type_i, impl::data_type_t type_o>
-using _qz_a1b0 = q10n::qz_a1b0<data_t<type_i>, data_t<type_o>>;
+using _qz_a1b0 = q10n::qz_a1b0_t<data_t<type_i>, data_t<type_o>>;
 
 template <impl::data_type_t type_i, impl::data_type_t type_o>
-using _qz = q10n::qz<data_t<type_i>, data_t<type_o>>;
+using _qz = q10n::qz_t<data_t<type_i>, data_t<type_o>>;
 
 namespace fmt_order {
 const bool keep = true;
@@ -343,7 +343,7 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                 const float s = src_scales[src_scales_mask == 0 ? 0 : os_off];
                 const float d = dst_scales[dst_scales_mask == 0 ? 0 : os_off];
 
-                o = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                o = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                         i, s * adj_scale * d);
                 if (req_comp) cp[g * OC + oc] -= (int32_t)o;
                 if (has_asymmetric_comp) zp[g * OC + oc] -= (int32_t)o;
@@ -547,7 +547,7 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                 const float src_scale = s[src_scales_mask == 0 ? 0 : os_off];
                 const float dst_scale = d[dst_scales_mask == 0 ? 0 : os_off];
                 out[index(oc, ic)]
-                        = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                        = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                                 inp[plain_off],
                                 src_scale * adj_scale * dst_scale);
                 if (req_comp) c[oc] -= (128 * (int32_t)(out[index(oc, ic)]));
@@ -710,7 +710,7 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
             for (dim_t oc = 0; oc < oc_block; ++oc) {
                 const auto plain_off
                         = oc * plain_d.blocking_desc().strides[w_groups + 0];
-                out[oc] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                out[oc] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                         inp[plain_off], s[oc] * adj_scale * d[oc]);
                 if (has_asymmetric_comp) zp[oc] -= (int32_t)(out[oc]);
             }
@@ -904,7 +904,7 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                         + ic * plain_d.blocking_desc().strides[w_groups + 1];
                 auto index = AB_or_BC_blk_off<tag_traits_t<tag_o>::inner_blks>(
                         oc, ic);
-                out[index] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                out[index] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                         inp[plain_off], s[oc] * adj_scale * d[oc]);
 
                 if (has_asymmetric_comp) zp[oc] -= (int32_t)(out[index]);
@@ -1077,8 +1077,9 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                     auto index
                             = AB_or_BC_blk_off<tag_traits_t<tag_o>::inner_blks>(
                                     d0, d1);
-                    out[index] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
-                            inp[plain_off], s[0] * adj_scale * d[0]);
+                    out[index]
+                            = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
+                                    inp[plain_off], s[0] * adj_scale * d[0]);
 
                     auto o = static_cast<int32_t>(out[index]);
                     if (req_comp) cp[d1] -= (128 * o);
@@ -1088,16 +1089,17 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                     auto index
                             = AB_or_BC_blk_off<tag_traits_t<tag_o>::inner_blks>(
                                     d0, d1);
-                    out[index] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
-                            0, s[0] * adj_scale * d[0]);
+                    out[index]
+                            = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
+                                    0, s[0] * adj_scale * d[0]);
                 }
             }
 
             for_(int d0 = d0_block; d0 < D0_blksize; ++d0)
             for (int d1 = 0; d1 < D1_blksize; ++d1) {
                 auto index = AB_or_BC_blk_off<tag_traits_t<tag_o>::inner_blks>(
                         d0, d1);
-                out[index] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                out[index] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                         0, s[0] * adj_scale * d[0]);
             }
         };
@@ -1265,7 +1267,7 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                         = src_scales[src_scales_mask == 0 ? 0 : g * OC];
                 const float dst_scale
                         = dst_scales[dst_scales_mask == 0 ? 0 : g * OC];
-                out[g] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                out[g] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                         inp[i_off], src_scale * adj_scale * dst_scale);
             }
         };
@@ -2094,25 +2096,26 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
             if (alpha == 1.0 && beta == 0.0) {
                 PRAGMA_OMP_SIMD()
                 for (size_t e = start; e < end; ++e) {
-                    output[e] = q10n::qz_a1b0<data_t<type_i>, data_t<type_o>>()(
-                            input[e]);
+                    output[e]
+                            = q10n::qz_a1b0_t<data_t<type_i>, data_t<type_o>>()(
+                                    input[e]);
                 }
             } else if (alpha == 1.0) {
                 PRAGMA_OMP_SIMD()
                 for (size_t e = start; e < end; ++e) {
-                    output[e] = q10n::qz_a1<data_t<type_i>, data_t<type_o>>()(
+                    output[e] = q10n::qz_a1_t<data_t<type_i>, data_t<type_o>>()(
                             input[e], output[e], beta);
                 }
             } else if (beta == 0.0) {
                 PRAGMA_OMP_SIMD()
                 for (size_t e = start; e < end; ++e) {
-                    output[e] = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
+                    output[e] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
                             input[e], alpha);
                 }
             } else {
                 PRAGMA_OMP_SIMD()
                 for (size_t e = start; e < end; ++e) {
-                    output[e] = q10n::qz<data_t<type_i>, data_t<type_o>>()(
+                    output[e] = q10n::qz_t<data_t<type_i>, data_t<type_o>>()(
                             input[e], output[e], alpha, beta);
                 }
             }
@@ -2121,28 +2124,27 @@ struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
                 if (alpha == 1.0 && beta == 0.0) {
                     PRAGMA_OMP_SIMD()
                     for (size_t e = nelems - rem_elems; e < nelems; ++e) {
-                        output[e] = q10n::qz_a1b0<data_t<type_i>,
+                        output[e] = q10n::qz_a1b0_t<data_t<type_i>,
                                 data_t<type_o>>()(input[e]);
                     }
                 } else if (alpha == 1.0) {
                     PRAGMA_OMP_SIMD()
                     for (size_t e = nelems - rem_elems; e < nelems; ++e) {
-                        output[e]
-                                = q10n::qz_a1<data_t<type_i>, data_t<type_o>>()(
-                                        input[e], output[e], beta);
+                        output[e] = q10n::qz_a1_t<data_t<type_i>,
+                                data_t<type_o>>()(input[e], output[e], beta);
                     }
                 } else if (beta == 0.0) {
                     PRAGMA_OMP_SIMD()
                     for (size_t e = nelems - rem_elems; e < nelems; ++e) {
-                        output[e]
-                                = q10n::qz_b0<data_t<type_i>, data_t<type_o>>()(
-                                        input[e], alpha);
+                        output[e] = q10n::qz_b0_t<data_t<type_i>,
+                                data_t<type_o>>()(input[e], alpha);
                     }
                 } else {
                     PRAGMA_OMP_SIMD()
                     for (size_t e = nelems - rem_elems; e < nelems; ++e) {
-                        output[e] = q10n::qz<data_t<type_i>, data_t<type_o>>()(
-                                input[e], output[e], alpha, beta);
+                        output[e]
+                                = q10n::qz_t<data_t<type_i>, data_t<type_o>>()(
+                                        input[e], output[e], alpha, beta);
                     }
                 }
             }

src/cpu/rnn/postgemm_dispatcher.hpp

@@ -253,20 +253,25 @@ struct rnn_postgemm_dispatcher {
                 && !mayiuse(avx512_core))
             return status::success;
 
+//NOLINTBEGIN(bugprone-macro-parentheses)
+// Can't put types into `()`:
+// error: expected type-specifier before ‘)’ token
 #define CREATE_WITH_DIR(k, ker_t) \
     do { \
         if (mayiuse(avx512_core)) \
-            k.reset(new ker_t<avx512_core, src_type, scratch_type>(rnn, pd_)); \
+            (k).reset( \
+                    new ker_t<avx512_core, src_type, scratch_type>(rnn, pd_)); \
         else if (mayiuse(avx2)) \
-            k.reset(new ker_t<avx2, src_type, scratch_type>(rnn, pd_)); \
+            (k).reset(new ker_t<avx2, src_type, scratch_type>(rnn, pd_)); \
         else \
-            k.reset(new ker_t<sse41, src_type, scratch_type>(rnn, pd_)); \
+            (k).reset(new ker_t<sse41, src_type, scratch_type>(rnn, pd_)); \
     } while (0)
 #define CREATE(k, ker_t) \
     do { \
-        if (jit_fwd) CREATE_WITH_DIR(k, CONCAT2(ker_t, _fwd)); \
-        if (jit_bwd) CREATE_WITH_DIR(k, CONCAT2(ker_t, _bwd)); \
+        if (jit_fwd) CREATE_WITH_DIR((k), CONCAT2(ker_t, _fwd)); \
+        if (jit_bwd) CREATE_WITH_DIR((k), CONCAT2(ker_t, _bwd)); \
     } while (0)
+        //NOLINTEND(bugprone-macro-parentheses)
 
         if (pd_->cell_kind() == alg_kind::vanilla_lstm) {
             CREATE(rnn_postgemm_, jit_uni_lstm_cell_postgemm);