Enable NETC support for i.MX95 EKV M7

boards/nxp/imx95_evk/CMakeLists.txt

@@ -11,3 +11,6 @@ if (CONFIG_SOF AND CONFIG_BOARD_IMX95_EVK_MIMX9596_M7_DDR)
     DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
   )
 endif()
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/nxp/imx95_evk/board.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <soc.h>
+
+static int board_init(void)
+{
+#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
+	/* Port 0 to 2 protocol configure: RGMII, RGMII, XGMII */
+	BLK_CTRL_NETCMIX->CFG_LINK_MII_PROT = 0x00000522;
+	BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_2 = 0x00000040;
+
+	/* Unlock the IERB. It will warm reset whole NETC. */
+	NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK;
+	while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) {
+	}
+
+	/* Lock the IERB. */
+	NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK;
+	while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) {
+	}
+#endif
+	return 0;
+}
+
+/*
+ * Because platform is using ARM SCMI, drivers like scmi, mbox etc. are
+ * initialized during PRE_KERNEL_1. Common init hooks is not able to use.
+ * SoC early init and board early init could be run during PRE_KERNEL_2 instead.
+ */
+SYS_INIT(board_init, PRE_KERNEL_2, 10);

boards/nxp/imx95_evk/doc/index.rst

@@ -96,6 +96,8 @@ The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardwar
 +-----------+------------+-------------------------------------+
 | GPIO      | on-chip    | gpio                                |
 +-----------+------------+-------------------------------------+
+| NETC      | on-chip    | ethernet, mdio                      |
++-----------+------------+-------------------------------------+
 
 The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
 the following hardware features:
@@ -145,6 +147,13 @@ SPI
 The EVK board need to be reworked to solder R1217/R1218/R1219/R1220 with 0R resistances.
 SPI1 on J35 is enabled for M7.
 
+Ethernet
+--------
+
+NETC driver supports to manage the Physical Station Interface (PSI).
+The first ENET1 port could be enabled for M7 by west build option
+``-DEXTRA_DTC_OVERLAY_FILE=enetc_psi0.overlay``.
+
 
 Programming and Debugging (A55)
 *******************************

boards/nxp/imx95_evk/dts/enetc_psi0.overlay

@@ -0,0 +1,17 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&emdio {
+	status = "okay";
+
+	phy0: phy@1 {
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	status = "okay";
+};

boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi

@@ -6,6 +6,42 @@
 #include <nxp/nxp_imx/mimx9596avzxn-pinctrl.dtsi>
 
 &pinctrl {
+	emdio_default: emdio_default {
+		group1 {
+			pinmux = <&iomuxc_enet1_mdc_netc_mdc_netc_mdc>,
+				<&iomuxc_enet1_mdio_netc_mdio_netc_mdio>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x6";
+		};
+	};
+
+	eth0_default: eth0_default {
+		group1 {
+			pinmux = <&iomuxc_enet1_rx_ctl_eth_rgmii_rx_ctl_eth0_rgmii_rx_ctl>,
+				<&iomuxc_enet1_rd0_eth_rgmii_rd_eth0_rgmii_rd0>,
+				<&iomuxc_enet1_rd1_eth_rgmii_rd_eth0_rgmii_rd1>,
+				<&iomuxc_enet1_rd2_eth_rgmii_rd_eth0_rgmii_rd2>,
+				<&iomuxc_enet1_rd3_eth_rgmii_rd_eth0_rgmii_rd3>,
+				<&iomuxc_enet1_tx_ctl_eth_rgmii_tx_ctl_eth0_rgmii_tx_ctl>,
+				<&iomuxc_enet1_td0_eth_rgmii_td_eth0_rgmii_td0>,
+				<&iomuxc_enet1_td1_eth_rgmii_td_eth0_rgmii_td1>,
+				<&iomuxc_enet1_td2_eth_rgmii_td_eth0_rgmii_td2>,
+				<&iomuxc_enet1_td3_eth_rgmii_td_eth0_rgmii_td3>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x6";
+		};
+		group2 {
+			pinmux = <&iomuxc_enet1_rxc_eth_rgmii_rx_clk_eth0_rgmii_rx_clk>,
+				<&iomuxc_enet1_txc_eth_rgmii_tx_clk_eth0_rgmii_tx_clk>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "x6";
+		};
+
+	};
+
 	lpi2c5_default: lpi2c5_default {
 		group0 {
 			pinmux = <&iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl>,

boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts

@@ -23,6 +23,27 @@
 	};
 };
 
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+
+	phy0: phy@1 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x1>;
+		status = "disabled";
+	};
+};
+
+&enetc_psi0 {
+	local-mac-address = [00 00 00 01 02 00];
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-connection-type = "rgmii";
+	status = "disabled";
+};
+
 &lpi2c5 {
 	pinctrl-0 = <&lpi2c5_default>;
 	pinctrl-names = "default";

boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml

@@ -18,4 +18,5 @@ supported:
   - i2c
   - pwm
   - spi
+  - netif:eth
 vendor: nxp

drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_priv.h

@@ -29,12 +29,20 @@
 /* MSGINTR */
 #define NETC_MSGINTR_CHANNEL 0
 
+#if DT_IRQ_HAS_IDX(DT_NODELABEL(netc), 0)
+#define NETC_MSGINTR_IRQ DT_IRQN_BY_IDX(DT_NODELABEL(netc), 0)
+#endif
+
 #if (CONFIG_ETH_NXP_IMX_MSGINTR == 1)
-#define NETC_MSGINTR     MSGINTR1
+#define NETC_MSGINTR MSGINTR1
+#ifndef NETC_MSGINTR_IRQ
 #define NETC_MSGINTR_IRQ MSGINTR1_IRQn
+#endif
 #elif (CONFIG_ETH_NXP_IMX_MSGINTR == 2)
-#define NETC_MSGINTR     MSGINTR2
+#define NETC_MSGINTR MSGINTR2
+#ifndef NETC_MSGINTR_IRQ
 #define NETC_MSGINTR_IRQ MSGINTR2_IRQn
+#endif
 #else
 #error "Current CONFIG_ETH_NXP_IMX_MSGINTR not support"
 #endif

dts/arm/nxp/nxp_imx95_m7.dtsi

@@ -50,6 +50,12 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			scmi_devpd: protocol@11 {
+				compatible = "arm,scmi-power";
+				reg = <0x11>;
+				#power-domain-cells = <1>;
+			};
+
 			scmi_clk: protocol@14 {
 				compatible = "arm,scmi-clock";
 				reg = <0x14>;
@@ -467,6 +473,64 @@
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
+
+		irqsteer: interrupt-controller@44680000 {
+			compatible = "nxp,irqsteer-intc";
+			reg = <0x44680000 DT_SIZE_K(64)>;
+
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			irqsteer_master0: interrupt-controller@0 {
+				compatible = "nxp,irqsteer-master";
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupts-extended = <&nvic 224 0>;
+			};
+		};
+
+		netc: ethernet@4ca00000 {
+			reg = <0x4ca00000 0x1000000>;
+			interrupt-parent = <&irqsteer_master0>;
+			interrupts = <13 0 0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			emdio: mdio@4cce0000 {
+				compatible = "nxp,imx-netc-emdio";
+				reg = <0x4cce0000 0x1c44>;
+				clocks = <&scmi_clk IMX95_CLK_ENET>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			enetc_psi0: ethernet@4cc00000 {
+				compatible = "nxp,imx-netc-psi";
+				reg = <0x4cc00000 0x10000>;
+				mac-index = <0>;
+				si-index = <0>;
+				status = "disabled";
+			};
+
+			enetc_psi1: ethernet@4cc40000 {
+				compatible = "nxp,imx-netc-psi";
+				reg = <0x4cc40000 0x10000>;
+				mac-index = <1>;
+				si-index = <1>;
+				status = "disabled";
+			};
+
+			enetc_psi2: ethernet@4cc80000 {
+				compatible = "nxp,imx-netc-psi";
+				reg = <0x4cc80000 0x10000>;
+				mac-index = <2>;
+				si-index = <2>;
+				status = "disabled";
+			};
+		};
 	};
 };
 

include/zephyr/dt-bindings/power/imx95_power.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX95_POWER_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX95_POWER_H_
+
+#define IMX95_PD_ANA       0
+#define IMX95_PD_AON       1
+#define IMX95_PD_BBSM      2
+#define IMX95_PD_CAMERA    3
+#define IMX95_PD_CCMSRCGPC 4
+#define IMX95_PD_A55C0     5
+#define IMX95_PD_A55C1     6
+#define IMX95_PD_A55C2     7
+#define IMX95_PD_A55C3     8
+#define IMX95_PD_A55C4     9
+#define IMX95_PD_A55C5     10
+#define IMX95_PD_A55P      11
+#define IMX95_PD_DDR       12
+#define IMX95_PD_DISPLAY   13
+#define IMX95_PD_GPU       14
+#define IMX95_PD_HSIO_TOP  15
+#define IMX95_PD_HSIO_WAON 16
+#define IMX95_PD_M7        17
+#define IMX95_PD_NETC      18
+#define IMX95_PD_NOC       19
+#define IMX95_PD_NPU       20
+#define IMX95_PD_VPU       21
+#define IMX95_PD_WAKEUP    22
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX95_POWER_H_ */

soc/nxp/imx/imx9/imx95/Kconfig

@@ -12,6 +12,7 @@ config SOC_MIMX9596_M7
 	select ARM_MPU
 	select SOC_LATE_INIT_HOOK
 	select HAS_MCUX
+	select HAS_MCUX_CACHE
 
 config SOC_MIMX9596_A55
 	select ARM64

soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7

@@ -11,13 +11,44 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
 
+# multi-level interrupts
+config MULTI_LEVEL_INTERRUPTS
+	default y
+
+config 1ST_LEVEL_INTERRUPT_BITS
+	default 8
+
+config MAX_IRQ_PER_AGGREGATOR
+	default 16
+
+config 2ND_LEVEL_INTERRUPTS
+	default y
+
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 234
+
+config NUM_2ND_LEVEL_AGGREGATORS
+	default 1
+
+config 2ND_LEVEL_INTERRUPT_BITS
+	default 8
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 224
+
+config 3RD_LEVEL_INTERRUPTS
+	default n
+
 config NUM_IRQS
-	default 230
+	default 250 # 2ND_LVL_ISR_TBL_OFFSET + MAX_IRQ_PER_AGGREGATOR * NUM_2ND_LEVEL_AGGREGATORS
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 800000000
 
 config CACHE_MANAGEMENT
 	default y
 
+config ETH_NXP_IMX_MSGINTR
+	default 2
+
 endif # SOC_MIMX9596_M7